Matches in DBpedia 2016-04 for { <http://wikidata.dbpedia.org/resource/Q16928029> ?p ?o }
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- Q16928029 subject Q6901441.
- Q16928029 subject Q7189892.
- Q16928029 subject Q7191538.
- Q16928029 subject Q7372759.
- Q16928029 subject Q7466576.
- Q16928029 subject Q7947474.
- Q16928029 abstract "In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors. The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995. No x86 motherboard was released with OpenPIC however. After the OpenPIC's failure in the x86 market, AMD licensed the Intel APIC Architecture for its AMD Athlon and later processors.IBM however developed their MultiProcessor Interrupt Controller (MPIC) based on the OpenPIC register specification. In the reference IBM design, the processors share the MPIC over a DCR bus, with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources. Through various implementations, the MPIC was included in PowerPC reference designs and some retail computers.IBM used a MPIC based on OpenPIC 1.0 in their RS/6000 F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual 8259 on their PCI-ISA bridges. An IBM MPIC was also used in the RS/6000 7046 Model B50.The Apple Hydra Mac I/O (MIO) chip (from the 1990s Mac OS era) implemented a MPIC alongside a SCSI controller, ADB controller, GeoPort controller, and timers. The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the Common Hardware Reference Platform was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources. A MPIC was also incorporated in the newer K2 I/O controller used in the Power Mac G5s.Freescale also uses a MPIC ("compatible with the Open PIC") on all its PowerQUICC and QorIQ processors. The Linux Kernel-based Virtual Machine (KVM) supports a virtualized MPIC with up to 256 interrupts, based on the Freescale variants.".
- Q16928029 wikiPageExternalLink AppleMPIC.
- Q16928029 wikiPageWikiLink Q1116130.
- Q16928029 wikiPageWikiLink Q128896.
- Q16928029 wikiPageWikiLink Q1502767.
- Q16928029 wikiPageWikiLink Q1547313.
- Q16928029 wikiPageWikiLink Q1565903.
- Q16928029 wikiPageWikiLink Q1756494.
- Q16928029 wikiPageWikiLink Q1801201.
- Q16928029 wikiPageWikiLink Q209860.
- Q16928029 wikiPageWikiLink Q213423.
- Q16928029 wikiPageWikiLink Q220868.
- Q16928029 wikiPageWikiLink Q2258920.
- Q16928029 wikiPageWikiLink Q2348942.
- Q16928029 wikiPageWikiLink Q248.
- Q16928029 wikiPageWikiLink Q312.
- Q16928029 wikiPageWikiLink Q324603.
- Q16928029 wikiPageWikiLink Q37156.
- Q16928029 wikiPageWikiLink Q377539.
- Q16928029 wikiPageWikiLink Q379711.
- Q16928029 wikiPageWikiLink Q390562.
- Q16928029 wikiPageWikiLink Q43627.
- Q16928029 wikiPageWikiLink Q621236.
- Q16928029 wikiPageWikiLink Q6901441.
- Q16928029 wikiPageWikiLink Q7189892.
- Q16928029 wikiPageWikiLink Q7191538.
- Q16928029 wikiPageWikiLink Q7372759.
- Q16928029 wikiPageWikiLink Q7466576.
- Q16928029 wikiPageWikiLink Q747489.
- Q16928029 wikiPageWikiLink Q7947474.
- Q16928029 wikiPageWikiLink Q846651.
- Q16928029 wikiPageWikiLink Q863675.
- Q16928029 wikiPageWikiLink Q941021.
- Q16928029 comment "In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors. The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995. No x86 motherboard was released with OpenPIC however.".
- Q16928029 label "OpenPIC and MPIC".