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- Q1424524 subject Q7662241.
- Q1424524 subject Q8728768.
- Q1424524 abstract "Shallow trench isolation (STI), also known as Box Isolation Technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization.[1]Certain semiconductor fabrication technologies also include deep trench isolation, a related feature often found in analog integrated circuits.The effect of the trench edge has given rise to what has recently been termed the "reverse narrow channel effect" or "inverse narrow width effect". Basically, due to the electric field enhancement at the edge, it is easier to form a conducting channel (by inversion) at a lower voltage. The threshold voltage is effectively reduced for a narrower transistor width. The main concern for electronic devices is the resulting subthreshold leakage current, which is substantially larger after the threshold voltage reduction.".
- Q1424524 thumbnail Isolation_pitch_vs_design_rule.PNG?width=300.
- Q1424524 wikiPageExternalLink features.htm.
- Q1424524 wikiPageExternalLink Using-broadband-reflectometry-for-fast-trench-depth-measurement.
- Q1424524 wikiPageExternalLink shallowtrenchisa.html.
- Q1424524 wikiPageExternalLink etronics_spin_stiov.asp.
- Q1424524 wikiPageWikiLink Q1050773.
- Q1424524 wikiPageWikiLink Q1069404.
- Q1424524 wikiPageWikiLink Q116269.
- Q1424524 wikiPageWikiLink Q11651.
- Q1424524 wikiPageWikiLink Q1570432.
- Q1424524 wikiPageWikiLink Q1658601.
- Q1424524 wikiPageWikiLink Q173431.
- Q1424524 wikiPageWikiLink Q1754002.
- Q1424524 wikiPageWikiLink Q175805.
- Q1424524 wikiPageWikiLink Q1798244.
- Q1424524 wikiPageWikiLink Q1811428.
- Q1424524 wikiPageWikiLink Q184996.
- Q1424524 wikiPageWikiLink Q2368605.
- Q1424524 wikiPageWikiLink Q3233153.
- Q1424524 wikiPageWikiLink Q46221.
- Q1424524 wikiPageWikiLink Q5505856.
- Q1424524 wikiPageWikiLink Q7662241.
- Q1424524 wikiPageWikiLink Q80831.
- Q1424524 wikiPageWikiLink Q8728768.
- Q1424524 comment "Shallow trench isolation (STI), also known as Box Isolation Technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.STI is created early during the semiconductor device fabrication process, before transistors are formed.".
- Q1424524 label "Shallow trench isolation".
- Q1424524 depiction Isolation_pitch_vs_design_rule.PNG.