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- Q1139187 subject Q7217113.
- Q1139187 subject Q7236458.
- Q1139187 subject Q8425924.
- Q1139187 abstract "The Cray T3E was Cray Research's second-generation massively parallel supercomputer architecture, launched in late November 1995. The first T3E was installed at the Pittsburgh Supercomputing Center in 1996. Like the previous Cray T3D, it was a fully distributed memory machine using a 3D torus topology interconnection network. The T3E initially used the DEC Alpha 21164 (EV5) microprocessor and was designed to scale from 8 to 2,176 Processing Elements (PEs). Each PE had between 64 MB and 2 GB of DRAM and a 6-way interconnect router with a payload bandwidth of 480 MB/s in each direction. Unlike many other MPP systems, including the T3D, the T3E was fully self-hosted and ran the UNICOS/mk distributed operating system with a GigaRing I/O subsystem integrated into the torus for network, disk and tape I/O.The original T3E (retrospectively known as the T3E-600) had a 300 MHz processor clock. Later variants, using the faster 21164A (EV56) processor, comprised the T3E-900 (450 MHz), T3E-1200 (600 MHz), T3E-1200E (with improved memory and interconnect performance) and T3E-1350 (675 MHz). The T3E was available in both air-cooled (AC) and liquid-cooled (LC) configurations. AC systems were available with 16 to 128 user PEs, LC systems with 64 to 2048 user PEs.A 1480-processor T3E-1200 was the first supercomputer to achieve a performance of more than 1 teraflops running a computational science application, in 1998. After Cray Research was acquired by Silicon Graphics in February 1996, development of new Alpha-based systems was stopped. While providing the -900, -1200 and -1200E upgrades to the T3E, in the long term Silicon Graphics intended Cray T3E users to migrate to the Origin 3000, a MIPS-based distributed shared memory computer, introduced in 2000. However, the T3E continued in production after SGI sold the Cray business the same year.".
- Q1139187 thumbnail T3E-900t.jpg?width=300.
- Q1139187 wikiPageExternalLink 4609.
- Q1139187 wikiPageExternalLink perf1200.html.
- Q1139187 wikiPageExternalLink t3e880.html.
- Q1139187 wikiPageWikiLink Q11042114.
- Q1139187 wikiPageWikiLink Q117801.
- Q1139187 wikiPageWikiLink Q1229610.
- Q1139187 wikiPageWikiLink Q144060.
- Q1139187 wikiPageWikiLink Q1752081.
- Q1139187 wikiPageWikiLink Q188768.
- Q1139187 wikiPageWikiLink Q189396.
- Q1139187 wikiPageWikiLink Q3277607.
- Q1139187 wikiPageWikiLink Q39369.
- Q1139187 wikiPageWikiLink Q527464.
- Q1139187 wikiPageWikiLink Q5297.
- Q1139187 wikiPageWikiLink Q544384.
- Q1139187 wikiPageWikiLink Q588145.
- Q1139187 wikiPageWikiLink Q623459.
- Q1139187 wikiPageWikiLink Q637619.
- Q1139187 wikiPageWikiLink Q690079.
- Q1139187 wikiPageWikiLink Q7199401.
- Q1139187 wikiPageWikiLink Q7217113.
- Q1139187 wikiPageWikiLink Q7236458.
- Q1139187 wikiPageWikiLink Q7390068.
- Q1139187 wikiPageWikiLink Q7827452.
- Q1139187 wikiPageWikiLink Q8425924.
- Q1139187 comment "The Cray T3E was Cray Research's second-generation massively parallel supercomputer architecture, launched in late November 1995. The first T3E was installed at the Pittsburgh Supercomputing Center in 1996. Like the previous Cray T3D, it was a fully distributed memory machine using a 3D torus topology interconnection network. The T3E initially used the DEC Alpha 21164 (EV5) microprocessor and was designed to scale from 8 to 2,176 Processing Elements (PEs).".
- Q1139187 label "Cray T3E".
- Q1139187 depiction T3E-900t.jpg.