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• Timing_closure abstract "Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.Nevertheless, even if timing-awareness was extended to all these steps starting from well-established principles used for logic synthesis, the two phases, logic and physical, of the timing closure process are conventionally handled by different design teams and different EDA tools. Design Compiler by Synopsys, Encounter RTL Compiler by Cadence Design Systems and BlastCreate by Magma Design Automation are examples of logic synthesis tools. IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.A timing requirement needs to be translated into a static timing constraint for an EDA tool to be able to handle it.".
• Timing_closure wikiPageExternalLink docs_timingclosure.html.
• Timing_closure wikiPageExternalLink index.aspx.
• Timing_closure wikiPageExternalLink index.aspx.
• Timing_closure wikiPageExternalLink BlastCreate.html.
• Timing_closure wikiPageExternalLink blastfusion.html.
• Timing_closure wikiPageExternalLink iccompiler.html.
• Timing_closure wikiPageExternalLink design_compiler.html.
• Timing_closure wikiPageID "7024370".
• Timing_closure wikiPageLength "2481".
• Timing_closure wikiPageOutDegree "14".
• Timing_closure wikiPageRevisionID "693575533".
• Timing_closure wikiPageWikiLink Category:Timing_in_electronic_circuits.
• Timing_closure wikiPageWikiLink Design_closure.
• Timing_closure wikiPageWikiLink Design_flow_(EDA).
• Timing_closure wikiPageWikiLink Electronic_design_automation.
• Timing_closure wikiPageWikiLink Field-programmable_gate_array.
• Timing_closure wikiPageWikiLink Integrated_circuit.
• Timing_closure wikiPageWikiLink Integrated_circuit_design.
• Timing_closure wikiPageWikiLink Placement_(EDA).
• Timing_closure wikiPageWikiLink Routing_(electronic_design_automation).
• Timing_closure wikiPageWikiLink Static_timing_analysis.
• Timing_closure wikiPageWikiLink Timing_closure.
• Timing_closure wikiPageWikiLinkText "Timing closure".
• Timing_closure wikiPageWikiLinkText "timing closure".
• Timing_closure wikiPageWikiLinkText "timing".
• Timing_closure wikiPageUsesTemplate Template:Context.
• Timing_closure wikiPageUsesTemplate Template:Multiple_issues.
• Timing_closure wikiPageUsesTemplate Template:Technical.
• Timing_closure subject Category:Timing_in_electronic_circuits.
• Timing_closure hypernym Process.
• Timing_closure type Election.
• Timing_closure type Circuit.
• Timing_closure type Page.
• Timing_closure type Redirect.
• Timing_closure comment "Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing.".
• Timing_closure label "Timing closure".
• Timing_closure sameAs Q7806736.
• Timing_closure sameAs m.0h0vr6.
• Timing_closure sameAs Q7806736.
• Timing_closure sameAs 时序收敛.
• Timing_closure wasDerivedFrom Timing_closure?oldid=693575533.
• Timing_closure isPrimaryTopicOf Timing_closure.