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- Structured_ASIC_platform abstract "Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA.Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease.In a FPGA, interconnects and logic blocks are programmable after fabrication, offering high flexibility of design and ease of debugging in prototyping.However, the capability of FPGAs to implement large circuits is limited, in both size and speed, due to complexity in programmable routing, and significant space occupied by programming elements, e.g. SRAMs, MUXes.On the other hand, ASIC design flow is expensive.Every different design needs a complete different set of masks.The Structured ASIC is a solution between these two.It has basically the same structure as a FPGA, but being mask-programmable instead of field-programmable, by configuring one or several via layers between metal layers.Every SRAM configuration bit can be replaced by a choice of putting a via or not between metal contacts. A number of commercial vendors have introduced structured ASIC products. They have a wide range of configurability, from a single via layer to 6 metal and 6 via layers. Altera's Hardcopy-II, eASIC's Nextreme are examples of commercial structured ASICs.".
- Structured_ASIC_platform wikiPageExternalLink ASICslides.ppt.
- Structured_ASIC_platform wikiPageID "18426062".
- Structured_ASIC_platform wikiPageLength "3367".
- Structured_ASIC_platform wikiPageOutDegree "8".
- Structured_ASIC_platform wikiPageRevisionID "620752357".
- Structured_ASIC_platform wikiPageWikiLink Altera.
- Structured_ASIC_platform wikiPageWikiLink Application-specific_integrated_circuit.
- Structured_ASIC_platform wikiPageWikiLink Category:Electronic_circuits.
- Structured_ASIC_platform wikiPageWikiLink Category:Logic_design.
- Structured_ASIC_platform wikiPageWikiLink EASIC.
- Structured_ASIC_platform wikiPageWikiLink Field-programmable_gate_array.
- Structured_ASIC_platform wikiPageWikiLink Gate_array.
- Structured_ASIC_platform wikiPageWikiLink Non-recurring_engineering.
- Structured_ASIC_platform wikiPageWikiLinkText "structured ASIC".
- Structured_ASIC_platform wikiPageUsesTemplate Template:More_footnotes.
- Structured_ASIC_platform wikiPageUsesTemplate Template:No_footnotes.
- Structured_ASIC_platform subject Category:Electronic_circuits.
- Structured_ASIC_platform subject Category:Logic_design.
- Structured_ASIC_platform hypernym Technology.
- Structured_ASIC_platform type Company.
- Structured_ASIC_platform type Circuit.
- Structured_ASIC_platform comment "Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA.Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease.In a FPGA, interconnects and logic blocks are programmable after fabrication, offering high flexibility of design and ease of debugging in prototyping.However, the capability of FPGAs to implement large circuits is limited, in both size and speed, due to complexity in programmable routing, and significant space occupied by programming elements, e.g. ".
- Structured_ASIC_platform label "Structured ASIC platform".
- Structured_ASIC_platform sameAs Q7625166.
- Structured_ASIC_platform sameAs m.04dzqln.
- Structured_ASIC_platform sameAs Q7625166.
- Structured_ASIC_platform wasDerivedFrom Structured_ASIC_platform?oldid=620752357.
- Structured_ASIC_platform isPrimaryTopicOf Structured_ASIC_platform.