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- Runway_bus abstract "The Runway bus is a front side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family. The Runway bus is a 64-bit wide, split transaction, time multiplexed address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive. The Runway bus was introduced with the release of the PA-7200 and was subsequently used by the PA-8000, PA-8200, PA-8500, PA-8600 and PA-8700 microprocessors. Early implementations of the bus used in the PA-7200, PA-8000 and PA-8200 had a theoretical bandwidth of 960 MB/s. Beginning with the PA-8500, the Runway bus was revised to transmit on both rising and falling edges of a 125 MHz clock signal, which increased its theoretical bandwidth to 2 GB/s. The Runway bus was succeeded with the introduction of the PA-8800, which used the Itanium 2 bus.Bus features 64-bit multiplexed address/data 20 bus protocol signals Supports cache coherency Three frequency options (1.0, 0.75 and 0.67 of CPU clock — 0.50 apparently was later added) Parity protection on address/data and control signal Each attached device contains its own arbitrator logic Split transactions, up to six transactions can be pending at once Snooping cache coherency protocol 1-4 processors \"glueless\" multi-processing (no support chips needed) 768 MB/s sustainable throughput, peak 960 MB/s at 120 MHz Runway+/Runway DDR: On PA-8500, PA-8600 and PA-8700, the bus operates in DDR (double data rate) mode, resulting in a peak bandwidth of about 2.0 GB/s (Runway+ or Runway DDR) with 125 MHzMost machines use the Runway bus to connect the CPUs directly to the IOMMU (Astro, U2/Uturn or Java) and memory.However, the N class and L3000 servers use an interface chip called Dew to bridge the Runway bus to the Merced bus that connects to the IOMMU and memory.".
- Runway_bus wikiPageExternalLink feb96a2.pdf.
- Runway_bus wikiPageID "1154386".
- Runway_bus wikiPageLength "2732".
- Runway_bus wikiPageOutDegree "18".
- Runway_bus wikiPageRevisionID "682725296".
- Runway_bus wikiPageWikiLink Category:Computer_buses.
- Runway_bus wikiPageWikiLink Category:Hewlett-Packard_products.
- Runway_bus wikiPageWikiLink Central_processing_unit.
- Runway_bus wikiPageWikiLink Computer_data_storage.
- Runway_bus wikiPageWikiLink Front-side_bus.
- Runway_bus wikiPageWikiLink Hewlett-Packard.
- Runway_bus wikiPageWikiLink Input–output_memory_management_unit.
- Runway_bus wikiPageWikiLink Itanium.
- Runway_bus wikiPageWikiLink Microprocessor.
- Runway_bus wikiPageWikiLink Microprocessor_Report.
- Runway_bus wikiPageWikiLink PA-7200.
- Runway_bus wikiPageWikiLink PA-8000.
- Runway_bus wikiPageWikiLink PA-RISC.
- Runway_bus wikiPageWikiLink Time-division_multiplexing.
- Runway_bus wikiPageWikiLinkText "Runway bus".
- Runway_bus wikiPageUsesTemplate Template:Cite_journal.
- Runway_bus wikiPageUsesTemplate Template:Computer-bus.
- Runway_bus wikiPageUsesTemplate Template:Reflist.
- Runway_bus subject Category:Computer_buses.
- Runway_bus subject Category:Hewlett-Packard_products.
- Runway_bus hypernym Bus.
- Runway_bus type Automobile.
- Runway_bus type Connector.
- Runway_bus type Product.
- Runway_bus type Protocol.
- Runway_bus comment "The Runway bus is a front side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family. The Runway bus is a 64-bit wide, split transaction, time multiplexed address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive.".
- Runway_bus label "Runway bus".
- Runway_bus sameAs Q7380142.
- Runway_bus sameAs m.04bvhf.
- Runway_bus sameAs Q7380142.
- Runway_bus wasDerivedFrom Runway_bus?oldid=682725296.
- Runway_bus isPrimaryTopicOf Runway_bus.