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- Cray_MTA abstract "The Cray MTA, formerly known as the Tera MTA, is a supercomputer architecture based on thousands of independent threads, fine-grain communication and synchronization between threads, and latency tolerance for irregular computations.Each MTA processor (CPU) has a high-performance ALU with many independent register sets, each running an independent thread. For example, the Cray MTA-2 uses 128 register sets and thus 128 threads per CPU/ALU. All MTAs to date use a barrel processor arrangement, with a thread switch on every cycle, with blocked (stalled) threads skipped to avoid wasting ALU cycles. When a thread performs a memory read, execution blocks until data returns; meanwhile, other threads continue executing. With enough threads (concurrency), there are nearly always runable threads to \"cover\" for blocked threads, and the ALUs stay busy. The memory system uses full/empty bits to ensure correct ordering. For example, an array A is initially written with \"empty\" bits, and any thread reading a value from A blocks until another thread writes a value. This ensures correct ordering, but allows fine-grained interleaving and provides a simple programming model. The memory system is also \"randomized\", with adjacent physical addresses going to different memory banks. Thus, when two threads access memory simultaneously, they rarely conflict unless they are accessing the same location.A goal of the MTA is that porting codes from other machines is straightforward, but gives good performance. A parallelizing FORTRAN compiler can produce high performance for some codes with little manual intervention. Where manual porting is required, the simple and fine-grained synchronization model often allows programmers to write code the \"obvious\" way yet achieve good performance. A further goal is that programs for the MTA will be scalable -- that is, when run on an MTA with twice as many CPUs, the same program will have nearly twice the performance. Both of these are challenges for many other high-performance computer systems.An uncommon feature of the MTA is several workloads can be interleaved with good performance. Typically, supercomputers are dedicated to a task at a time. The MTA allows idle threads to be allocated to other tasks with very little effect on the main calculations.".
- Cray_MTA wikiPageExternalLink CrayXMTSystem.aspx.
- Cray_MTA wikiPageID "25458359".
- Cray_MTA wikiPageLength "7095".
- Cray_MTA wikiPageOutDegree "18".
- Cray_MTA wikiPageRevisionID "654055613".
- Cray_MTA wikiPageWikiLink Arithmetic_logic_unit.
- Cray_MTA wikiPageWikiLink Barrel_processor.
- Cray_MTA wikiPageWikiLink CMOS.
- Cray_MTA wikiPageWikiLink Category:Cray_products.
- Cray_MTA wikiPageWikiLink Category:Supercomputers.
- Cray_MTA wikiPageWikiLink Central_processing_unit.
- Cray_MTA wikiPageWikiLink Compiler.
- Cray_MTA wikiPageWikiLink Cray_MTA-2.
- Cray_MTA wikiPageWikiLink Cray_XMT.
- Cray_MTA wikiPageWikiLink Fortran.
- Cray_MTA wikiPageWikiLink empty_bits.
- Cray_MTA wikiPageWikiLink Gallium_arsenide.
- Cray_MTA wikiPageWikiLink Heterogeneous_Element_Processor.
- Cray_MTA wikiPageWikiLink San_Diego_Supercomputer_Center.
- Cray_MTA wikiPageWikiLink Scalability.
- Cray_MTA wikiPageWikiLink Supercomputer.
- Cray_MTA wikiPageWikiLink United_States_Naval_Research_Laboratory.
- Cray_MTA wikiPageWikiLinkText "Cray MTA".
- Cray_MTA wikiPageWikiLinkText "MTA".
- Cray_MTA wikiPageUsesTemplate Template:Reflist.
- Cray_MTA subject Category:Cray_products.
- Cray_MTA subject Category:Supercomputers.
- Cray_MTA hypernym Architecture.
- Cray_MTA type Company.
- Cray_MTA type Class.
- Cray_MTA type Product.
- Cray_MTA type Supercomputer.
- Cray_MTA comment "The Cray MTA, formerly known as the Tera MTA, is a supercomputer architecture based on thousands of independent threads, fine-grain communication and synchronization between threads, and latency tolerance for irregular computations.Each MTA processor (CPU) has a high-performance ALU with many independent register sets, each running an independent thread. For example, the Cray MTA-2 uses 128 register sets and thus 128 threads per CPU/ALU.".
- Cray_MTA label "Cray MTA".
- Cray_MTA sameAs Q5183021.
- Cray_MTA sameAs m.09k4nyp.
- Cray_MTA sameAs Q5183021.
- Cray_MTA wasDerivedFrom Cray_MTA?oldid=654055613.
- Cray_MTA isPrimaryTopicOf Cray_MTA.