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- AMD_Horus abstract "The Horus system, designed by Newisys for AMD, was created to enable AMD Opteron machines to extend beyond the current limit of 8-way (CPU sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport (ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets. The HyperTransport bus is also distance restricted and does not permit off-system interconnect.The Horus system overcomes these limitations by creating a pseudo-Opteron, the Horus chip, which connects to four real Opterons via the HyperTransport bus. As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad'). The Horus chip then provides an additional off-board interface (based on the InfiniBand standards) which can link to additional Horus nodes (up to 8). The chip handles the necessary translation between local and off-board ccHT communications. By building the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding), this system has an effective internal speed of 30 Gbit/s. With 8 'quads' connected together, each with the maximum of four Opteron sockets per node, the Horus system allows a total of 32 CPU sockets in a single machine. Dual and future quad-core chips will also be supported, allowing a single system to scale to over a hundred processing cores.".
- AMD_Horus wikiPageExternalLink 27ca34ceb63c0472?safe=images&ie=UTF-8&as_umsgid=788a2f10.0408310718.6524dfe9@posting.google.com&lr=&hl=en.
- AMD_Horus wikiPageExternalLink horus_external_white_paper_final.pdf.
- AMD_Horus wikiPageID "3044880".
- AMD_Horus wikiPageLength "2034".
- AMD_Horus wikiPageOutDegree "10".
- AMD_Horus wikiPageRevisionID "684276474".
- AMD_Horus wikiPageWikiLink 10b_encoding.
- AMD_Horus wikiPageWikiLink Advanced_Micro_Devices.
- AMD_Horus wikiPageWikiLink Category:Advanced_Micro_Devices_technologies.
- AMD_Horus wikiPageWikiLink Category:Computer_buses.
- AMD_Horus wikiPageWikiLink Central_processing_unit.
- AMD_Horus wikiPageWikiLink Heterogeneous_System_Architecture.
- AMD_Horus wikiPageWikiLink HyperTransport.
- AMD_Horus wikiPageWikiLink InfiniBand.
- AMD_Horus wikiPageWikiLink Newisys.
- AMD_Horus wikiPageWikiLink Opteron.
- AMD_Horus wikiPageWikiLinkText "AMD Horus".
- AMD_Horus wikiPageWikiLinkText "HORUS interconnect".
- AMD_Horus wikiPageUsesTemplate Template:AMD_processors.
- AMD_Horus subject Category:Advanced_Micro_Devices_technologies.
- AMD_Horus subject Category:Computer_buses.
- AMD_Horus type Company.
- AMD_Horus type Company.
- AMD_Horus type Connector.
- AMD_Horus type Protocol.
- AMD_Horus comment "The Horus system, designed by Newisys for AMD, was created to enable AMD Opteron machines to extend beyond the current limit of 8-way (CPU sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport (ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets.".
- AMD_Horus label "AMD Horus".
- AMD_Horus sameAs Q4032953.
- AMD_Horus sameAs m.08mvf0.
- AMD_Horus sameAs AMD_Horus.
- AMD_Horus sameAs Q4032953.
- AMD_Horus wasDerivedFrom AMD_Horus?oldid=684276474.
- AMD_Horus isPrimaryTopicOf AMD_Horus.