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- Q175376 subject Q9711069.
- Q175376 abstract "The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.".
- Q175376 wikiPageExternalLink books?id=ACxTAAAAMAAJ&q=cmos+vlsi+design&dq=cmos+vlsi+design.
- Q175376 wikiPageWikiLink Q173431.
- Q175376 wikiPageWikiLink Q4531332.
- Q175376 wikiPageWikiLink Q4817329.
- Q175376 wikiPageWikiLink Q4934059.
- Q175376 wikiPageWikiLink Q5253471.
- Q175376 wikiPageWikiLink Q570553.
- Q175376 wikiPageWikiLink Q62866.
- Q175376 wikiPageWikiLink Q9711069.
- Q175376 comment "The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.".
- Q175376 label "Logical effort".