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- 31116.pdf accessdate "2014-01-09".
- 31116.pdf accessdate "2015-04-09".
- 31116.pdf date "2013-01-11".
- 31116.pdf format "PDF".
- 31116.pdf isCitedBy Long_mode.
- 31116.pdf isCitedBy Multi-channel_memory_architecture.
- 31116.pdf page "107–108".
- 31116.pdf page "30".
- 31116.pdf publisher "amd.com".
- 31116.pdf quote "Physical address space increased to 48 bits.".
- 31116.pdf quote "When the DCTs are in ganged mode, as specified by [The DRAM Controller Select Low Register] F2x110 [DctGangEn], then each logical DIMM is two channels wide. Each physical DIMM of a 2-channel logical DIMM is required to be the same size and use the same timing parameters. Both DCTs must be programmed with the same information . When the DCTs are in unganged mode, a logical DIMM is equivalent to a 64-bit physical DIMM and each channel is controlled by a different DCT. Typical systems are recommended to run in unganged mode to benefit from the additional parallelism generated by using the DCTs independently. See 2.12.2 [DRAM Considerations for ECC] for DRAM ECC implications of ganged and unganged mode. Ganged mode is not supported for S1g3, S1g4, ASB2, and G34 processors.".
- 31116.pdf title "36000.0".
- 31116.pdf url 31116.pdf.