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- tcs.1979.1084695 doi "10.1109/TCS.1979.1084695".
- tcs.1979.1084695 first1 "Tatsuo".
- tcs.1979.1084695 first2 "Hajimu".
- tcs.1979.1084695 first3 "Ernest S.".
- tcs.1979.1084695 first4 "Toshinobu".
- tcs.1979.1084695 first5 "Toshio".
- tcs.1979.1084695 isCitedBy List_of_NP-complete_problems.
- tcs.1979.1084695 isCitedBy Pathwidth.
- tcs.1979.1084695 issue "9".
- tcs.1979.1084695 journal "IEEE Transactions on Circuits and Systems".
- tcs.1979.1084695 last1 "Ohtsuki".
- tcs.1979.1084695 last2 "Mori".
- tcs.1979.1084695 last3 "Kuh".
- tcs.1979.1084695 last4 "Kashiwabara".
- tcs.1979.1084695 last5 "Fujisawa".
- tcs.1979.1084695 pages "675–684".
- tcs.1979.1084695 ref "harv".
- tcs.1979.1084695 title "One-dimensional logic gate assignment and interval graphs".
- tcs.1979.1084695 volume "26".
- tcs.1979.1084695 year "1979".