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- Standard_cell abstract "In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology — the general class to which standard cells belong — makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.".
- Standard_cell thumbnail Silicon_chip_3d.png?width=300.
- Standard_cell wikiPageExternalLink freepdk.ecen.okstate.edu.
- Standard_cell wikiPageExternalLink www.chipx.com.
- Standard_cell wikiPageExternalLink book.
- Standard_cell wikiPageExternalLink low-power-standard-cell-design.
- Standard_cell wikiPageExternalLink www.vlsitechnology.org.
- Standard_cell wikiPageExternalLink cell.php.
- Standard_cell wikiPageID "1936117".
- Standard_cell wikiPageLength "14546".
- Standard_cell wikiPageOutDegree "62".
- Standard_cell wikiPageRevisionID "694356003".
- Standard_cell wikiPageWikiLink 130_nanometer.
- Standard_cell wikiPageWikiLink AND_gate.
- Standard_cell wikiPageWikiLink Adder_(electronics).
- Standard_cell wikiPageWikiLink Application-specific_integrated_circuit.
- Standard_cell wikiPageWikiLink Boolean_algebra.
- Standard_cell wikiPageWikiLink CMOS.
- Standard_cell wikiPageWikiLink Category:Electronic_design_automation.
- Standard_cell wikiPageWikiLink Category:Logic_gates.
- Standard_cell wikiPageWikiLink Circuit_design.
- Standard_cell wikiPageWikiLink Complex_programmable_logic_device.
- Standard_cell wikiPageWikiLink Computer-aided_design.
- Standard_cell wikiPageWikiLink Configurator.
- Standard_cell wikiPageWikiLink Design_rule_checking.
- Standard_cell wikiPageWikiLink Electronic_design_automation.
- Standard_cell wikiPageWikiLink Exclusive_or.
- Standard_cell wikiPageWikiLink Field-programmable_gate_array.
- Standard_cell wikiPageWikiLink File:Eda-fabrication.PNG.
- Standard_cell wikiPageWikiLink Foundry.
- Standard_cell wikiPageWikiLink Gate_equivalent.
- Standard_cell wikiPageWikiLink Graphical_user_interface.
- Standard_cell wikiPageWikiLink High-level_synthesis.
- Standard_cell wikiPageWikiLink Integrated_circuit.
- Standard_cell wikiPageWikiLink Integrated_circuit_layout.
- Standard_cell wikiPageWikiLink Layout_Versus_Schematic.
- Standard_cell wikiPageWikiLink Liberty_(EDA).
- Standard_cell wikiPageWikiLink Library_Exchange_Format.
- Standard_cell wikiPageWikiLink Logic_synthesis.
- Standard_cell wikiPageWikiLink NAND_gate.
- Standard_cell wikiPageWikiLink Netlist.
- Standard_cell wikiPageWikiLink OR_gate.
- Standard_cell wikiPageWikiLink Parasitic_extraction.
- Standard_cell wikiPageWikiLink Place_and_route.
- Standard_cell wikiPageWikiLink Placement_(EDA).
- Standard_cell wikiPageWikiLink Register-transfer_level.
- Standard_cell wikiPageWikiLink Routing_(electronic_design_automation).
- Standard_cell wikiPageWikiLink SPICE.
- Standard_cell wikiPageWikiLink Semiconductor.
- Standard_cell wikiPageWikiLink Semiconductor_device_fabrication.
- Standard_cell wikiPageWikiLink Sequential_logic.
- Standard_cell wikiPageWikiLink Spectre_Circuit_Simulator.
- Standard_cell wikiPageWikiLink Spice_model.
- Standard_cell wikiPageWikiLink State_transition_table.
- Standard_cell wikiPageWikiLink Synopsys.
- Standard_cell wikiPageWikiLink System_on_a_chip.
- Standard_cell wikiPageWikiLink Truth_table.
- Standard_cell wikiPageWikiLink VHDL-VITAL.
- Standard_cell wikiPageWikiLink Verilog.
- Standard_cell wikiPageWikiLink Very-large-scale_integration.
- Standard_cell wikiPageWikiLink XNOR_gate.
- Standard_cell wikiPageWikiLink File:Silicon_chip_3d.png.
- Standard_cell wikiPageWikiLinkText "Standard cell".
- Standard_cell wikiPageWikiLinkText "Standard_cell#Library".
- Standard_cell wikiPageWikiLinkText "standard cell libraries".
- Standard_cell wikiPageWikiLinkText "standard cell library".
- Standard_cell wikiPageWikiLinkText "standard cell".
- Standard_cell wikiPageWikiLinkText "standard library cells".
- Standard_cell wikiPageWikiLinkText "standard-cell".
- Standard_cell wikiPageUsesTemplate Template:Digital_systems.
- Standard_cell wikiPageUsesTemplate Template:For.
- Standard_cell wikiPageUsesTemplate Template:Jargon.
- Standard_cell wikiPageUsesTemplate Template:Unreferenced.
- Standard_cell subject Category:Electronic_design_automation.
- Standard_cell subject Category:Logic_gates.
- Standard_cell hypernym Method.
- Standard_cell type Software.
- Standard_cell type Circuit.
- Standard_cell type Redirect.
- Standard_cell comment "In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).".
- Standard_cell label "Standard cell".
- Standard_cell sameAs Q464496.
- Standard_cell sameAs Standardzelle.
- Standard_cell sameAs 표준셀.
- Standard_cell sameAs m.067c5z.
- Standard_cell sameAs Standard_cell.
- Standard_cell sameAs Q464496.
- Standard_cell wasDerivedFrom Standard_cell?oldid=694356003.
- Standard_cell depiction Silicon_chip_3d.png.
- Standard_cell isPrimaryTopicOf Standard_cell.