Matches in DBpedia 2016-04 for { <http://dbpedia.org/resource/OpenRISC_1200> ?p ?o }
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- OpenRISC_1200 abstract "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- OpenRISC_1200 thumbnail OR1200.png?width=300.
- OpenRISC_1200 wikiPageExternalLink openrisc1200_spec.pdf.
- OpenRISC_1200 wikiPageExternalLink openrisc,architecture.
- OpenRISC_1200 wikiPageExternalLink Implementation_information.
- OpenRISC_1200 wikiPageExternalLink UClibc_tool_chain_test_results.
- OpenRISC_1200 wikiPageExternalLink openrisc.html.
- OpenRISC_1200 wikiPageExternalLink Free-32-bit-processor-core-hits-the-Net.
- OpenRISC_1200 wikiPageExternalLink openrisc,or1200.
- OpenRISC_1200 wikiPageExternalLink ?s=devkit.
- OpenRISC_1200 wikiPageID "16732958".
- OpenRISC_1200 wikiPageLength "4899".
- OpenRISC_1200 wikiPageOutDegree "34".
- OpenRISC_1200 wikiPageRevisionID "671518932".
- OpenRISC_1200 wikiPageWikiLink ARM_architecture.
- OpenRISC_1200 wikiPageWikiLink Application-specific_integrated_circuit.
- OpenRISC_1200 wikiPageWikiLink CPU_cache.
- OpenRISC_1200 wikiPageWikiLink Category:Open_microprocessors.
- OpenRISC_1200 wikiPageWikiLink Category:Soft_microprocessors.
- OpenRISC_1200 wikiPageWikiLink Coremark.
- OpenRISC_1200 wikiPageWikiLink Dhrystone.
- OpenRISC_1200 wikiPageWikiLink Digital_signal_processor.
- OpenRISC_1200 wikiPageWikiLink Field-programmable_gate_array.
- OpenRISC_1200 wikiPageWikiLink GNU_Compiler_Collection.
- OpenRISC_1200 wikiPageWikiLink GNU_Lesser_General_Public_License.
- OpenRISC_1200 wikiPageWikiLink GNU_toolchain.
- OpenRISC_1200 wikiPageWikiLink Hardware_description_language.
- OpenRISC_1200 wikiPageWikiLink Harvard_architecture.
- OpenRISC_1200 wikiPageWikiLink IEEE_floating_point.
- OpenRISC_1200 wikiPageWikiLink Instruction_set.
- OpenRISC_1200 wikiPageWikiLink Linux_kernel.
- OpenRISC_1200 wikiPageWikiLink Memory_management_unit.
- OpenRISC_1200 wikiPageWikiLink Multiply–accumulate_operation.
- OpenRISC_1200 wikiPageWikiLink Newlib.
- OpenRISC_1200 wikiPageWikiLink OpenCores.
- OpenRISC_1200 wikiPageWikiLink OpenRISC.
- OpenRISC_1200 wikiPageWikiLink Open_source.
- OpenRISC_1200 wikiPageWikiLink Programmable_Interrupt_Controller.
- OpenRISC_1200 wikiPageWikiLink Reduced_instruction_set_computing.
- OpenRISC_1200 wikiPageWikiLink Semiconductor_intellectual_property_core.
- OpenRISC_1200 wikiPageWikiLink Soft_microprocessor.
- OpenRISC_1200 wikiPageWikiLink Translation_lookaside_buffer.
- OpenRISC_1200 wikiPageWikiLink UClibc.
- OpenRISC_1200 wikiPageWikiLink Verilog.
- OpenRISC_1200 wikiPageWikiLink Wishbone_(computer_bus).
- OpenRISC_1200 wikiPageWikiLink File:OR1200.png.
- OpenRISC_1200 wikiPageWikiLink File:OR1200_cpu.png.
- OpenRISC_1200 wikiPageWikiLinkText "OpenRISC 1200".
- OpenRISC_1200 wikiPageWikiLinkText "OpenRISC_1200".
- OpenRISC_1200 wikiPageUsesTemplate Template:Citation_needed.
- OpenRISC_1200 wikiPageUsesTemplate Template:Portal.
- OpenRISC_1200 wikiPageUsesTemplate Template:Programmable_Logic.
- OpenRISC_1200 wikiPageUsesTemplate Template:Reflist.
- OpenRISC_1200 subject Category:Open_microprocessors.
- OpenRISC_1200 subject Category:Soft_microprocessors.
- OpenRISC_1200 hypernym Implementation.
- OpenRISC_1200 type Software.
- OpenRISC_1200 type Redirect.
- OpenRISC_1200 comment "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- OpenRISC_1200 label "OpenRISC 1200".
- OpenRISC_1200 sameAs Q7095862.
- OpenRISC_1200 sameAs m.0404hlb.
- OpenRISC_1200 sameAs Q7095862.
- OpenRISC_1200 wasDerivedFrom OpenRISC_1200?oldid=671518932.
- OpenRISC_1200 depiction OR1200.png.
- OpenRISC_1200 isPrimaryTopicOf OpenRISC_1200.