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- Memory-level_parallelism abstract "Memory-level parallelism (MLP) is a term in computer architecture referring to the ability to have pending multiple memory operations, in particular cache misses or translation lookaside buffer (TLB) misses, at the same time.In a single processor, MLP may be considered a form of instruction-level parallelism (ILP). However, ILP is often conflated with superscalar, the ability to execute more than one instruction at the same time. E.g., a processor such as the Intel Pentium Pro is five-way superscalar, with the ability to start executing five different microinstructions in a given cycle, but it can handle four different cache misses for up to 20 different load microinstructions at any time.It is possible to have a machine that is not superscalar but which nevertheless has high MLP. Arguably a machine that has no ILP, which is not superscalar, which executes one instruction at a time in a non-pipelined manner, but which performs hardware prefetching (not software instruction level prefetching) exhibits MLP (due to multiple prefetches outstanding) but not ILP. This is because there are multiple memory operations outstanding, but not instructions. Instructions are often conflated with operations.Furthermore, multiprocessor and multithreaded computer systems may be said to exhibit MLP and ILP due to parallelism—but not intra-thread, single process, ILP and MLP. Often, however, we restrict the terms MLP and ILP to refer to extracting such parallelism from what appears to be non-parallel single threaded code.".
- Memory-level_parallelism wikiPageExternalLink andrew_glew.pdf.
- Memory-level_parallelism wikiPageExternalLink andrew_glew.pdf.
- Memory-level_parallelism wikiPageID "12064843".
- Memory-level_parallelism wikiPageLength "4592".
- Memory-level_parallelism wikiPageOutDegree "17".
- Memory-level_parallelism wikiPageRevisionID "679414057".
- Memory-level_parallelism wikiPageWikiLink CPU_cache.
- Memory-level_parallelism wikiPageWikiLink Category:Instruction_processing.
- Memory-level_parallelism wikiPageWikiLink Category:Parallel_computing.
- Memory-level_parallelism wikiPageWikiLink Hardware_scout.
- Memory-level_parallelism wikiPageWikiLink Instruction-level_parallelism.
- Memory-level_parallelism wikiPageWikiLink International_Conference_on_High_Performance_Embedded_Architectures_and_Compilers.
- Memory-level_parallelism wikiPageWikiLink International_Supercomputing_Conference.
- Memory-level_parallelism wikiPageWikiLink International_Symposium_on_Computer_Architecture.
- Memory-level_parallelism wikiPageWikiLink Lecture_Notes_in_Computer_Science.
- Memory-level_parallelism wikiPageWikiLink Memory_dependence_prediction.
- Memory-level_parallelism wikiPageWikiLink Memory_disambiguation.
- Memory-level_parallelism wikiPageWikiLink Pentium_Pro.
- Memory-level_parallelism wikiPageWikiLink Proceedings_of_the_IEEE.
- Memory-level_parallelism wikiPageWikiLink Runahead.
- Memory-level_parallelism wikiPageWikiLink Superscalar_processor.
- Memory-level_parallelism wikiPageWikiLink Translation_lookaside_buffer.
- Memory-level_parallelism wikiPageWikiLinkText "Memory-level parallelism".
- Memory-level_parallelism wikiPageUsesTemplate Template:CPU_technologies.
- Memory-level_parallelism wikiPageUsesTemplate Template:Cite_book.
- Memory-level_parallelism wikiPageUsesTemplate Template:Cite_conference.
- Memory-level_parallelism wikiPageUsesTemplate Template:Cite_journal.
- Memory-level_parallelism wikiPageUsesTemplate Template:Citeseerx.
- Memory-level_parallelism wikiPageUsesTemplate Template:Parallel_Computing.
- Memory-level_parallelism subject Category:Instruction_processing.
- Memory-level_parallelism subject Category:Parallel_computing.
- Memory-level_parallelism hypernym Term.
- Memory-level_parallelism type Redirect.
- Memory-level_parallelism comment "Memory-level parallelism (MLP) is a term in computer architecture referring to the ability to have pending multiple memory operations, in particular cache misses or translation lookaside buffer (TLB) misses, at the same time.In a single processor, MLP may be considered a form of instruction-level parallelism (ILP). However, ILP is often conflated with superscalar, the ability to execute more than one instruction at the same time.".
- Memory-level_parallelism label "Memory-level parallelism".
- Memory-level_parallelism sameAs Q6815651.
- Memory-level_parallelism sameAs メモリレベルの並列性.
- Memory-level_parallelism sameAs m.02vnmvf.
- Memory-level_parallelism sameAs Паралелизам_на_нивоу_меморије.
- Memory-level_parallelism sameAs Q6815651.
- Memory-level_parallelism sameAs 記憶體層級平行.
- Memory-level_parallelism wasDerivedFrom Memory-level_parallelism?oldid=679414057.
- Memory-level_parallelism isPrimaryTopicOf Memory-level_parallelism.