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- ESi-RISC abstract "eSi-RISC is a configurable CPU architecture from Ensilica. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3260. The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.".
- ESi-RISC thumbnail ESi-3250.png?width=300.
- ESi-RISC wikiPageExternalLink risc-ip.
- ESi-RISC wikiPageID "25202651".
- ESi-RISC wikiPageLength "4438".
- ESi-RISC wikiPageOutDegree "31".
- ESi-RISC wikiPageRevisionID "665181060".
- ESi-RISC wikiPageWikiLink 16-bit.
- ESi-RISC wikiPageWikiLink 32-bit.
- ESi-RISC wikiPageWikiLink Advanced_Microcontroller_Bus_Architecture.
- ESi-RISC wikiPageWikiLink Application-specific_integrated_circuit.
- ESi-RISC wikiPageWikiLink C++_Standard_Library.
- ESi-RISC wikiPageWikiLink Category:Soft_microprocessors.
- ESi-RISC wikiPageWikiLink Central_processing_unit.
- ESi-RISC wikiPageWikiLink ERIKA_Enterprise.
- ESi-RISC wikiPageWikiLink Eclipse_(software).
- ESi-RISC wikiPageWikiLink EnSilica.
- ESi-RISC wikiPageWikiLink Field-programmable_gate_array.
- ESi-RISC wikiPageWikiLink FreeRTOS.
- ESi-RISC wikiPageWikiLink GNU_Binutils.
- ESi-RISC wikiPageWikiLink GNU_Compiler_Collection.
- ESi-RISC wikiPageWikiLink GNU_Debugger.
- ESi-RISC wikiPageWikiLink GNU_toolchain.
- ESi-RISC wikiPageWikiLink Integrated_development_environment.
- ESi-RISC wikiPageWikiLink Joint_Test_Action_Group.
- ESi-RISC wikiPageWikiLink Memory_management_unit.
- ESi-RISC wikiPageWikiLink Micro-Controller_Operating_Systems.
- ESi-RISC wikiPageWikiLink Multiprocessing.
- ESi-RISC wikiPageWikiLink Newlib.
- ESi-RISC wikiPageWikiLink Phoenix-RTOS.
- ESi-RISC wikiPageWikiLink Real-time_operating_system.
- ESi-RISC wikiPageWikiLink Reduced_instruction_set_computing.
- ESi-RISC wikiPageWikiLink SIMD.
- ESi-RISC wikiPageWikiLink Semiconductor_intellectual_property_core.
- ESi-RISC wikiPageWikiLink Soft_microprocessor.
- ESi-RISC wikiPageWikiLink File:ESi-3250.png.
- ESi-RISC wikiPageWikiLinkText "eSI-RISC".
- ESi-RISC wikiPageWikiLinkText "eSi-1600".
- ESi-RISC wikiPageWikiLinkText "eSi-3200".
- ESi-RISC wikiPageWikiLinkText "eSi-3250".
- ESi-RISC wikiPageWikiLinkText "eSi-RISC".
- ESi-RISC bits "16".
- ESi-RISC branching "Compare and branch and condition code".
- ESi-RISC design "RISC".
- ESi-RISC designer EnSilica.
- ESi-RISC encoding "Intermixed 16 and 32-bit".
- ESi-RISC endianness "Big or little".
- ESi-RISC extensions "User-defined instructions".
- ESi-RISC introduced "2009".
- ESi-RISC name "eSi-RISC".
- ESi-RISC registers "8".
- ESi-RISC type "Register-Register".
- ESi-RISC wikiPageUsesTemplate Template:Cleanup-list.
- ESi-RISC wikiPageUsesTemplate Template:Infobox_CPU_architecture.
- ESi-RISC wikiPageUsesTemplate Template:Lowercase.
- ESi-RISC wikiPageUsesTemplate Template:Multiple_issues.
- ESi-RISC wikiPageUsesTemplate Template:RISC-based_processor_architectures.
- ESi-RISC wikiPageUsesTemplate Template:Refimprove.
- ESi-RISC wikiPageUsesTemplate Template:Reflist.
- ESi-RISC wikiPageUsesTemplate Template:Use_dmy_dates.
- ESi-RISC subject Category:Soft_microprocessors.
- ESi-RISC hypernym Architecture.
- ESi-RISC type Company.
- ESi-RISC type Page.
- ESi-RISC comment "eSi-RISC is a configurable CPU architecture from Ensilica. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3260. The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.".
- ESi-RISC label "ESi-RISC".
- ESi-RISC sameAs Q5324414.
- ESi-RISC sameAs ESi-RISC.
- ESi-RISC sameAs ESi-RISC.
- ESi-RISC sameAs m.09gf4jn.
- ESi-RISC sameAs Q5324414.
- ESi-RISC wasDerivedFrom ESi-RISC?oldid=665181060.
- ESi-RISC depiction ESi-3250.png.
- ESi-RISC isPrimaryTopicOf ESi-RISC.