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- DLX abstract "The DLX (pronounced \"Deluxe\") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.There are two known implementations: ASPIDA and VAMP. ASPIDA project resulted in a core with many nice features: open source, supports Wishbone, asynchronous design, supports multiple ISA's, ASIC proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in Verilog, and runs on a Xilinx FPGA. A full stack from compiler to kernel to TCP/IP was built on it.".
- DLX wikiPageExternalLink project,aspida.
- DLX wikiPageExternalLink download;jsessionid=F3092E4572A237F069257DFF168CB07A?doi=10.1.1.217.2251&rep=rep1&type=pdf.
- DLX wikiPageExternalLink HERA.
- DLX wikiPageExternalLink windlx.html.
- DLX wikiPageExternalLink opendlx.
- DLX wikiPageExternalLink escape.
- DLX wikiPageExternalLink dlx.html.
- DLX wikiPageExternalLink dlx.php.
- DLX wikiPageExternalLink instructions.pdf.
- DLX wikiPageID "482305".
- DLX wikiPageLength "7178".
- DLX wikiPageOutDegree "33".
- DLX wikiPageRevisionID "706835719".
- DLX wikiPageWikiLink Arithmetic_logic_unit.
- DLX wikiPageWikiLink Berkeley_RISC.
- DLX wikiPageWikiLink Category:Educational_abstract_machines.
- DLX wikiPageWikiLink Category:Instruction_set_architectures.
- DLX wikiPageWikiLink Central_processing_unit.
- DLX wikiPageWikiLink Classic_RISC_pipeline.
- DLX wikiPageWikiLink Computer_architecture.
- DLX wikiPageWikiLink David_Patterson_(computer_scientist).
- DLX wikiPageWikiLink Endianness.
- DLX wikiPageWikiLink Floating-point_unit.
- DLX wikiPageWikiLink Instruction_pipelining.
- DLX wikiPageWikiLink Instruction_register.
- DLX wikiPageWikiLink John_L._Hennessy.
- DLX wikiPageWikiLink LC-3.
- DLX wikiPageWikiLink List_of_educational_programming_languages.
- DLX wikiPageWikiLink store_architecture.
- DLX wikiPageWikiLink MDMX.
- DLX wikiPageWikiLink MIPS-3D.
- DLX wikiPageWikiLink MIPS_instruction_set.
- DLX wikiPageWikiLink MIX.
- DLX wikiPageWikiLink MMIX.
- DLX wikiPageWikiLink MicroBlaze.
- DLX wikiPageWikiLink MikroSim.
- DLX wikiPageWikiLink Morgan_Kaufmann_Publishers.
- DLX wikiPageWikiLink NOP.
- DLX wikiPageWikiLink Opcode.
- DLX wikiPageWikiLink OpenRISC.
- DLX wikiPageWikiLink Reduced_instruction_set_computing.
- DLX wikiPageWikiLink Register-Register.
- DLX wikiPageWikiLink University.
- DLX wikiPageWikiLinkText "DLX".
- DLX wikiPageWikiLinkText "DLX-like processor".
- DLX bits "32".
- DLX branching "Condition register".
- DLX design "RISC".
- DLX designer "John L. Hennessy and David A. Patterson".
- DLX encoding "Fixed".
- DLX endianness Endianness.
- DLX extensions "None, but MDMX & MIPS-3D could be used".
- DLX fpr "32".
- DLX gpr "31".
- DLX introduced "1990.0".
- DLX name "DLX".
- DLX open "Yes".
- DLX type store_architecture.
- DLX type Register-Register.
- DLX version "1".
- DLX wikiPageUsesTemplate Template:About.
- DLX wikiPageUsesTemplate Template:Cite_book.
- DLX wikiPageUsesTemplate Template:Infobox_CPU_architecture.
- DLX wikiPageUsesTemplate Template:RISC-based_processor_architectures.
- DLX subject Category:Educational_abstract_machines.
- DLX subject Category:Instruction_set_architectures.
- DLX hypernym Architecture.
- DLX type Company.
- DLX type Model.
- DLX type Architecture.
- DLX type Machine.
- DLX type Model.
- DLX type Architecture.
- DLX comment "The DLX (pronounced \"Deluxe\") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU.".
- DLX label "DLX".
- DLX sameAs Q362451.
- DLX sameAs DLX-Prozessor.
- DLX sameAs DLX.
- DLX sameAs DLX.
- DLX sameAs DLX.
- DLX sameAs DLX_(informatica).
- DLX sameAs DLX.
- DLX sameAs m.02ftdf.
- DLX sameAs DLX.
- DLX sameAs DLX_(arhitektura_procesora).
- DLX sameAs DLX_(архитектура_процесора).
- DLX sameAs DLX.
- DLX sameAs Q362451.
- DLX wasDerivedFrom DLX?oldid=706835719.
- DLX isPrimaryTopicOf DLX.