Matches in DBpedia 2016-04 for { <http://dbpedia.org/resource/CoreConnect> ?p ?o }
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- CoreConnect abstract "CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA bus architecture, allowing reuse of existing SoC-components.IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as Cadence, Ericsson, Lucent, Nokia, Siemens and Synopsys.The CoreConnect is an integral part of IBM's Power Architecture offering and is used extensively in their PowerPC 4x0 based designs. Xilinx uses CoreConnect as the infrastructure for all of their embedded processor designs even though only a few are Power Architecture based.".
- CoreConnect wikiPageExternalLink Index.cfm?AD=1&ArticleID=4089.
- CoreConnect wikiPageExternalLink DcrBus.pdf.
- CoreConnect wikiPageExternalLink crcon_ugl.html.
- CoreConnect wikiPageExternalLink ip_product_details.jsp?key=dr_pcentral_coreconnect.
- CoreConnect wikiPageExternalLink CoreConnect_Bus_Architecture.
- CoreConnect wikiPageID "13743910".
- CoreConnect wikiPageLength "3903".
- CoreConnect wikiPageOutDegree "27".
- CoreConnect wikiPageRevisionID "607132327".
- CoreConnect wikiPageWikiLink Advanced_Microcontroller_Bus_Architecture.
- CoreConnect wikiPageWikiLink Bit_rate.
- CoreConnect wikiPageWikiLink Bus_(computing).
- CoreConnect wikiPageWikiLink Cadence_Design_Systems.
- CoreConnect wikiPageWikiLink Category:Computer_buses.
- CoreConnect wikiPageWikiLink Category:Power_Architecture.
- CoreConnect wikiPageWikiLink Central_processing_unit.
- CoreConnect wikiPageWikiLink Design_point.
- CoreConnect wikiPageWikiLink Device_control_register.
- CoreConnect wikiPageWikiLink Ericsson.
- CoreConnect wikiPageWikiLink Gigabyte.
- CoreConnect wikiPageWikiLink IBM.
- CoreConnect wikiPageWikiLink Latency_(engineering).
- CoreConnect wikiPageWikiLink Lucent.
- CoreConnect wikiPageWikiLink Microprocessor.
- CoreConnect wikiPageWikiLink Multi-core_processor.
- CoreConnect wikiPageWikiLink Nokia.
- CoreConnect wikiPageWikiLink PowerPC_400.
- CoreConnect wikiPageWikiLink Power_Architecture.
- CoreConnect wikiPageWikiLink Processor_register.
- CoreConnect wikiPageWikiLink Siemens.
- CoreConnect wikiPageWikiLink Synchronization_(computer_science).
- CoreConnect wikiPageWikiLink Synopsys.
- CoreConnect wikiPageWikiLink System_on_a_chip.
- CoreConnect wikiPageWikiLink Xilinx.
- CoreConnect wikiPageWikiLinkText "CoreConnect bus".
- CoreConnect wikiPageWikiLinkText "CoreConnect".
- CoreConnect wikiPageWikiLinkText "DCR bus".
- CoreConnect wikiPageWikiLinkText "Device Control Register".
- CoreConnect wikiPageWikiLinkText "OPB".
- CoreConnect wikiPageWikiLinkText "PLB".
- CoreConnect wikiPageUsesTemplate Template:Computer-bus.
- CoreConnect wikiPageUsesTemplate Template:Power_Architecture.
- CoreConnect subject Category:Computer_buses.
- CoreConnect subject Category:Power_Architecture.
- CoreConnect hypernym Microprocessor.
- CoreConnect type Connector.
- CoreConnect type Protocol.
- CoreConnect comment "CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus.".
- CoreConnect label "CoreConnect".
- CoreConnect sameAs Q1801201.
- CoreConnect sameAs Processor_Local_Bus.
- CoreConnect sameAs Processor_Local_Bus.
- CoreConnect sameAs m.03cgx57.
- CoreConnect sameAs Q1801201.
- CoreConnect wasDerivedFrom CoreConnect?oldid=607132327.
- CoreConnect isPrimaryTopicOf CoreConnect.