Matches in DBpedia 2016-04 for { ?s ?p "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL)."@en }
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- OpenRISC_1200 abstract "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- Q7095862 abstract "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- OpenRISC_1200 comment "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- Q7095862 comment "The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".