Matches in DBpedia 2016-04 for { ?s ?p "Spacer patterning is a technique employed for patterning features with linewidths smaller than can be achieved by conventional lithography. In the most general sense, the spacer is a layer that is deposited over a pre-patterned feature, often called the mandrel. The spacer is subsequently etched back so that the spacer portion covering the mandrel is etched away while the spacer portion on the sidewall remains. The mandrel may then be removed, leaving two spacers (one for each edge) for each mandrel. The spacers may be further trimmed to narrower widths, especially to act as mandrels for a subsequent 2nd spacer formation. Hence this is a readily practiced form of multiple patterning. Alternatively, one of the two spacers may be removed and the remaining one trimmed to a much smaller final linewidth. Whereas immersion lithography has a resolution of ~40 nm lines and spaces, spacer patterning may be applied to attain 20 nm. This resolution improvement technique is also known as Self-Aligned Double Patterning (SADP). SADP may be re-applied for even higher resolution, and has already been demonstrated for 15 nm NAND flash memory. Spacer patterning has also been adopted for sub-20 nm logic nodes, e.g., 14 nm and 10 nm."@en }
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- Spacer_patterning abstract "Spacer patterning is a technique employed for patterning features with linewidths smaller than can be achieved by conventional lithography. In the most general sense, the spacer is a layer that is deposited over a pre-patterned feature, often called the mandrel. The spacer is subsequently etched back so that the spacer portion covering the mandrel is etched away while the spacer portion on the sidewall remains. The mandrel may then be removed, leaving two spacers (one for each edge) for each mandrel. The spacers may be further trimmed to narrower widths, especially to act as mandrels for a subsequent 2nd spacer formation. Hence this is a readily practiced form of multiple patterning. Alternatively, one of the two spacers may be removed and the remaining one trimmed to a much smaller final linewidth. Whereas immersion lithography has a resolution of ~40 nm lines and spaces, spacer patterning may be applied to attain 20 nm. This resolution improvement technique is also known as Self-Aligned Double Patterning (SADP). SADP may be re-applied for even higher resolution, and has already been demonstrated for 15 nm NAND flash memory. Spacer patterning has also been adopted for sub-20 nm logic nodes, e.g., 14 nm and 10 nm.".