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- XCore_XS1-L1 abstract "The XS1-L1is a 32-bit processor designed by XMOS, featuring support for up to 8 concurrent threads. It was available as of June 2009 running at 400 MHz. As of April 2010 500 MHz versions are available. Each thread can run at up to 125 MHz; four threads follow each other through the pipeline, resulting in a top speed of 500 MIPS if at least four threads are active. The 500 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.".
- XCore_XS1-L1 thumbnail XCore_XS1-L1_48QFP.png?width=300.
- XCore_XS1-L1 wikiPageExternalLink XM-000324-RF-1.pdf.
- XCore_XS1-L1 wikiPageID "23361937".
- XCore_XS1-L1 wikiPageLength "4826".
- XCore_XS1-L1 wikiPageOutDegree "25".
- XCore_XS1-L1 wikiPageRevisionID "609543926".
- XCore_XS1-L1 wikiPageWikiLink Barrier_(computer_science).
- XCore_XS1-L1 wikiPageWikiLink CPU_cache.
- XCore_XS1-L1 wikiPageWikiLink Category:Digital_signal_processors.
- XCore_XS1-L1 wikiPageWikiLink Category:Parallel_computing.
- XCore_XS1-L1 wikiPageWikiLink Channel_(programming).
- XCore_XS1-L1 wikiPageWikiLink Communicating_sequential_processes.
- XCore_XS1-L1 wikiPageWikiLink Compile_time.
- XCore_XS1-L1 wikiPageWikiLink Event_(computing).
- XCore_XS1-L1 wikiPageWikiLink Instruction_cache.
- XCore_XS1-L1 wikiPageWikiLink Instruction_pipeline.
- XCore_XS1-L1 wikiPageWikiLink Instruction_set.
- XCore_XS1-L1 wikiPageWikiLink Interrupt.
- XCore_XS1-L1 wikiPageWikiLink Interrupts.
- XCore_XS1-L1 wikiPageWikiLink Load-store_architecture.
- XCore_XS1-L1 wikiPageWikiLink store_architecture.
- XCore_XS1-L1 wikiPageWikiLink Microprocessor.
- XCore_XS1-L1 wikiPageWikiLink QFN.
- XCore_XS1-L1 wikiPageWikiLink QFP.
- XCore_XS1-L1 wikiPageWikiLink Quad_Flat_No-leads_package.
- XCore_XS1-L1 wikiPageWikiLink Quad_Flat_Package.
- XCore_XS1-L1 wikiPageWikiLink Semaphore_(programming).
- XCore_XS1-L1 wikiPageWikiLink Symmetric_multiprocessing.
- XCore_XS1-L1 wikiPageWikiLink XCore_XS1.
- XCore_XS1-L1 wikiPageWikiLink XMOS.
- XCore_XS1-L1 wikiPageWikiLink XSwitch.
- XCore_XS1-L1 wikiPageWikiLinkText "XCore XS1-L1".
- XCore_XS1-L1 wikiPageWikiLinkText "Xcore XS1-L".
- XCore_XS1-L1 arch XCore_XS1.
- XCore_XS1-L1 caption "An XMOS Xcore-L processor, 48 TQFP package, 7x7 mm.".
- XCore_XS1-L1 fastUnit "MHz".
- XCore_XS1-L1 fastest "500".
- XCore_XS1-L1 hasPhotoCollection XCore_XS1-L1.
- XCore_XS1-L1 name "XS1-L".
- XCore_XS1-L1 numcores "1".
- XCore_XS1-L1 pack "124".
- XCore_XS1-L1 pack "128".
- XCore_XS1-L1 pack "48".
- XCore_XS1-L1 pack "64".
- XCore_XS1-L1 producedStart "2009".
- XCore_XS1-L1 slowUnit "MHz".
- XCore_XS1-L1 wikiPageUsesTemplate Template:Infobox_CPU.
- XCore_XS1-L1 wikiPageUsesTemplate Template:Main.
- XCore_XS1-L1 wikiPageUsesTemplate Template:Reflist.
- XCore_XS1-L1 subject Category:Digital_signal_processors.
- XCore_XS1-L1 subject Category:Parallel_computing.
- XCore_XS1-L1 hypernym Processor.
- XCore_XS1-L1 type Software.
- XCore_XS1-L1 type Processor.
- XCore_XS1-L1 comment "The XS1-L1is a 32-bit processor designed by XMOS, featuring support for up to 8 concurrent threads. It was available as of June 2009 running at 400 MHz. As of April 2010 500 MHz versions are available. Each thread can run at up to 125 MHz; four threads follow each other through the pipeline, resulting in a top speed of 500 MIPS if at least four threads are active. The 500 MIPS of each core is equally distributed over all active threads.".
- XCore_XS1-L1 label "XCore XS1-L1".
- XCore_XS1-L1 sameAs m.06w82b_.
- XCore_XS1-L1 sameAs Q17145540.
- XCore_XS1-L1 sameAs Q17145540.
- XCore_XS1-L1 wasDerivedFrom XCore_XS1-L1?oldid=609543926.
- XCore_XS1-L1 depiction XCore_XS1-L1_48QFP.png.
- XCore_XS1-L1 isPrimaryTopicOf XCore_XS1-L1.