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- Digital_clock_manager abstract "A digital clock manager (DCM) is a feature available on some FPGAs (notably ones produced by Xilinx), for manipulating clock signals by: Multipling or dividing an incoming clock (DFS). Reconditioning a clock for a steady duty cycle duty cycle. Adding a phase shift using a Delay-locked loop Eliminating clock skew within an FPGA design.↑".
- Digital_clock_manager wikiPageID "12610397".
- Digital_clock_manager wikiPageLength "965".
- Digital_clock_manager wikiPageOutDegree "15".
- Digital_clock_manager wikiPageRevisionID "671389888".
- Digital_clock_manager wikiPageWikiLink Category:Digital_electronics.
- Digital_clock_manager wikiPageWikiLink Category:Electronic_design.
- Digital_clock_manager wikiPageWikiLink Category:Gate_arrays.
- Digital_clock_manager wikiPageWikiLink Category:Integrated_circuits.
- Digital_clock_manager wikiPageWikiLink Category:Oscillators.
- Digital_clock_manager wikiPageWikiLink Clock_signal.
- Digital_clock_manager wikiPageWikiLink Clock_skew.
- Digital_clock_manager wikiPageWikiLink Delay-locked_loop.
- Digital_clock_manager wikiPageWikiLink Duty_cycle.
- Digital_clock_manager wikiPageWikiLink FPGA.
- Digital_clock_manager wikiPageWikiLink Field-programmable_gate_array.
- Digital_clock_manager wikiPageWikiLink Phase-locked_loop.
- Digital_clock_manager wikiPageWikiLink Phase_(waves).
- Digital_clock_manager wikiPageWikiLink Phase_Shift.
- Digital_clock_manager wikiPageWikiLink Xilinx.
- Digital_clock_manager wikiPageWikiLinkText "Digital clock manager".
- Digital_clock_manager hasPhotoCollection Digital_clock_manager.
- Digital_clock_manager wikiPageUsesTemplate Template:Compu-stub.
- Digital_clock_manager wikiPageUsesTemplate Template:Context.
- Digital_clock_manager wikiPageUsesTemplate Template:Manual.
- Digital_clock_manager subject Category:Digital_electronics.
- Digital_clock_manager subject Category:Electronic_design.
- Digital_clock_manager subject Category:Gate_arrays.
- Digital_clock_manager subject Category:Integrated_circuits.
- Digital_clock_manager subject Category:Oscillators.
- Digital_clock_manager hypernym Feature.
- Digital_clock_manager type Work.
- Digital_clock_manager type Array.
- Digital_clock_manager type Circuit.
- Digital_clock_manager comment "A digital clock manager (DCM) is a feature available on some FPGAs (notably ones produced by Xilinx), for manipulating clock signals by: Multipling or dividing an incoming clock (DFS). Reconditioning a clock for a steady duty cycle duty cycle. Adding a phase shift using a Delay-locked loop Eliminating clock skew within an FPGA design.↑".
- Digital_clock_manager label "Digital clock manager".
- Digital_clock_manager sameAs m.02wxtbr.
- Digital_clock_manager sameAs Q5276052.
- Digital_clock_manager sameAs Q5276052.
- Digital_clock_manager wasDerivedFrom Digital_clock_manager?oldid=671389888.
- Digital_clock_manager isPrimaryTopicOf Digital_clock_manager.