Matches in DBpedia 2016-04 for { ?s ?p "Channel-Link (C-Link) by National Semiconductor is a high-speed interface for cost-effectively transferring data at rates from 250 megabits/second to 6.4 gigabits/second over backplanes or cables. National Semiconductor introduced the first Channel-Link chipsets in the late 1990s to provide an alternative to continually widening data buses to get higher throughput.Channel-Link uses LVDS, and comes in configurations with three, four, or eight parallel data transfer lanes plus the source-synchronized clock for each configuration. In cable applications, it uses one twisted pair in order to transmit a clock signal, and on the remaining differential pairs it transmits digital data at a bit rate that is seven times the frequency of the clock signal. The backplane applications work the same way except for using differential traces instead of twisted pairs.The three Channel-Link chipset configurations provide varying user interfaces. For example, the three-lane chipset has 21 single-ended inputs and outputs for the user interface, and the four-lane chipset has 28 single-ended inputs and outputs. The eight-lane chipset has 48 single ended inputs and outputs because it uses one of the 7 serialized bits/lane to DC-balance the other six bits."@en }
Showing triples 1 to 2 of
2
with 100 triples per page.
- Channel_Link abstract "Channel-Link (C-Link) by National Semiconductor is a high-speed interface for cost-effectively transferring data at rates from 250 megabits/second to 6.4 gigabits/second over backplanes or cables. National Semiconductor introduced the first Channel-Link chipsets in the late 1990s to provide an alternative to continually widening data buses to get higher throughput.Channel-Link uses LVDS, and comes in configurations with three, four, or eight parallel data transfer lanes plus the source-synchronized clock for each configuration. In cable applications, it uses one twisted pair in order to transmit a clock signal, and on the remaining differential pairs it transmits digital data at a bit rate that is seven times the frequency of the clock signal. The backplane applications work the same way except for using differential traces instead of twisted pairs.The three Channel-Link chipset configurations provide varying user interfaces. For example, the three-lane chipset has 21 single-ended inputs and outputs for the user interface, and the four-lane chipset has 28 single-ended inputs and outputs. The eight-lane chipset has 48 single ended inputs and outputs because it uses one of the 7 serialized bits/lane to DC-balance the other six bits.".
- Q5072416 abstract "Channel-Link (C-Link) by National Semiconductor is a high-speed interface for cost-effectively transferring data at rates from 250 megabits/second to 6.4 gigabits/second over backplanes or cables. National Semiconductor introduced the first Channel-Link chipsets in the late 1990s to provide an alternative to continually widening data buses to get higher throughput.Channel-Link uses LVDS, and comes in configurations with three, four, or eight parallel data transfer lanes plus the source-synchronized clock for each configuration. In cable applications, it uses one twisted pair in order to transmit a clock signal, and on the remaining differential pairs it transmits digital data at a bit rate that is seven times the frequency of the clock signal. The backplane applications work the same way except for using differential traces instead of twisted pairs.The three Channel-Link chipset configurations provide varying user interfaces. For example, the three-lane chipset has 21 single-ended inputs and outputs for the user interface, and the four-lane chipset has 28 single-ended inputs and outputs. The eight-lane chipset has 48 single ended inputs and outputs because it uses one of the 7 serialized bits/lane to DC-balance the other six bits.".