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- XCore_XS1-G4 abstract "The XS1-G4 is a processor designed by XMOS. It is a 32-bit quad-core processor, where each core runs up to 8 concurrent threads. It was available as of Autumn 2008 running at 400 MHz. Each thread can run at up to 100 MHz; four threads follow each other through the pipeline, resulting in a top speed of 1.6 GIPS for four cores if 16 threads are running. The XS1-G4 is a distributed memory multi core processor, requiring the end user and compiler to deal with data distribution. When more than 4 threads execute, the 400 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.".
- XCore_XS1-G4 thumbnail XCore_XS1-G4_144BGA.png?width=300.
- XCore_XS1-G4 wikiPageExternalLink XM-000324-RF-1.pdf.
- XCore_XS1-G4 wikiPageID "21159543".
- XCore_XS1-G4 wikiPageLength "4651".
- XCore_XS1-G4 wikiPageOutDegree "22".
- XCore_XS1-G4 wikiPageRevisionID "609544027".
- XCore_XS1-G4 wikiPageWikiLink Ball_grid_array.
- XCore_XS1-G4 wikiPageWikiLink CPU_cache.
- XCore_XS1-G4 wikiPageWikiLink Category:Digital_signal_processors.
- XCore_XS1-G4 wikiPageWikiLink Category:Parallel_computing.
- XCore_XS1-G4 wikiPageWikiLink Channel_(communications).
- XCore_XS1-G4 wikiPageWikiLink Compile_time.
- XCore_XS1-G4 wikiPageWikiLink Compiler.
- XCore_XS1-G4 wikiPageWikiLink Distributed_memory.
- XCore_XS1-G4 wikiPageWikiLink Event_(computing).
- XCore_XS1-G4 wikiPageWikiLink Instruction_cache.
- XCore_XS1-G4 wikiPageWikiLink Instruction_pipeline.
- XCore_XS1-G4 wikiPageWikiLink Instruction_set.
- XCore_XS1-G4 wikiPageWikiLink Interrupt.
- XCore_XS1-G4 wikiPageWikiLink Interrupts.
- XCore_XS1-G4 wikiPageWikiLink Load-store_architecture.
- XCore_XS1-G4 wikiPageWikiLink store_architecture.
- XCore_XS1-G4 wikiPageWikiLink Microprocessor.
- XCore_XS1-G4 wikiPageWikiLink Multi-core_processor.
- XCore_XS1-G4 wikiPageWikiLink Multi_core.
- XCore_XS1-G4 wikiPageWikiLink RAM.
- XCore_XS1-G4 wikiPageWikiLink Random-access_memory.
- XCore_XS1-G4 wikiPageWikiLink XCore_XS1.
- XCore_XS1-G4 wikiPageWikiLink XMOS.
- XCore_XS1-G4 wikiPageWikiLink XSwitch.
- XCore_XS1-G4 wikiPageWikiLinkText "XCore XS1-G4".
- XCore_XS1-G4 wikiPageWikiLinkText "XCore_XS1-G4".
- XCore_XS1-G4 arch XCore_XS1.
- XCore_XS1-G4 caption "An XMOS Xcore processor, 144 Ball grid array package, 12×12 mm.".
- XCore_XS1-G4 fastUnit "MHz".
- XCore_XS1-G4 hasPhotoCollection XCore_XS1-G4.
- XCore_XS1-G4 name "XS1-G4".
- XCore_XS1-G4 numcores "4".
- XCore_XS1-G4 pack "144".
- XCore_XS1-G4 pack "512".
- XCore_XS1-G4 producedStart "2008".
- XCore_XS1-G4 slowUnit "MHz".
- XCore_XS1-G4 slowest "400".
- XCore_XS1-G4 wikiPageUsesTemplate Template:Infobox_CPU.
- XCore_XS1-G4 wikiPageUsesTemplate Template:Main.
- XCore_XS1-G4 wikiPageUsesTemplate Template:Reflist.
- XCore_XS1-G4 subject Category:Digital_signal_processors.
- XCore_XS1-G4 subject Category:Parallel_computing.
- XCore_XS1-G4 hypernym Processor.
- XCore_XS1-G4 type Software.
- XCore_XS1-G4 type Processor.
- XCore_XS1-G4 comment "The XS1-G4 is a processor designed by XMOS. It is a 32-bit quad-core processor, where each core runs up to 8 concurrent threads. It was available as of Autumn 2008 running at 400 MHz. Each thread can run at up to 100 MHz; four threads follow each other through the pipeline, resulting in a top speed of 1.6 GIPS for four cores if 16 threads are running. The XS1-G4 is a distributed memory multi core processor, requiring the end user and compiler to deal with data distribution.".
- XCore_XS1-G4 label "XCore XS1-G4".
- XCore_XS1-G4 sameAs m.05b_thl.
- XCore_XS1-G4 sameAs Q8041727.
- XCore_XS1-G4 sameAs Q8041727.
- XCore_XS1-G4 wasDerivedFrom XCore_XS1-G4?oldid=609544027.
- XCore_XS1-G4 depiction XCore_XS1-G4_144BGA.png.
- XCore_XS1-G4 isPrimaryTopicOf XCore_XS1-G4.
